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| ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet Features * * Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs Provides a range of clock outputs: - 2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz * * * * 19.44 MHz (SONET/SDH) 1.544 MHz (DS1) and 3.088 MHz a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3) * * Ordering Information ZL30106QDG 64 pin TQFP -40C to +85C * * Selectable loop filter bandwidth of 29 Hz or 922 Hz Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253CORE OC-3 and G.813 STM-1 specifications Less than 0.6 nspp intrinsic jitter on all PDH output clocks and frame pulses Selectable external master clock source: clock oscillator or crystal Simple hardware control interface October 2004 * * * Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse Provides automatic entry into Holdover and return from Holdover Manual and automatic hitless reference switching Provides lock, holdover and accurate reference fail indication OSCi OSCo TIE_CLR Applications * * * Line card synchronization for SONET/SDH and PDH systems Wireless base-station Network Interface Card AdvancedTCATM and H.110 line cards BW_SEL LOCK OUT_SEL2 REF0 REF_SYNC0 REF1 REF_SYNC1 REF2 REF_FAIL0 REF_FAIL1 REF_FAIL2 APP_SEL1:0 Master Clock MUX TIE Corrector Circuit Virtual Reference DPLL E1 Synthesizer Reference Monitor TIE Corrector Enable DS1 Synthesizer Mode Control SDH Synthesizer Programmable Synthesizer REF_SEL1:0 RST State Machine Frequency Select MUX C2o C4/C65o C8/C32o C16o F4/F65o F8/F32o F16o C1.5o C3o C19o F2ko C6/8.4/34/44o OUT_SEL1:0 IEEE 1149.1a TRST MODE_SEL1:0 HMS HOLDOVER TCK TDI TMS TDO Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. ZL30106 Description Data Sheet The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards. The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs. The ZL30106 output clocks wander and jitter generation are compliant with the associated transport medium specifications. 2 Zarlink Semiconductor Inc. ZL30106 Table of Contents Data Sheet 1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Reference Select Multiplexer (MUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Application Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 Loop Filter and Limiter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Output Clock and Frame Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4.4 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.1 Manual Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.2 Automatic Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.2.1 Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.2.2 Automatic Reference Switching - Reference Frequency Out-of-Range . . . . . . . . . . . . . . . . . 26 4.6 Clock-and-Sync Pair Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.6 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.7 Pull-in Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.8 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.9 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3 Zarlink Semiconductor Inc. ZL30106 Table of Contents Data Sheet 8.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 Zarlink Semiconductor Inc. ZL30106 List of Figures Data Sheet Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - Behaviour of the Dis/Re-qualify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - Out-of-Range Thresholds for APP_SEL1:0=00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6 - Out-of-Range Thresholds for APP_SEL1:0=01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Out-of-Range Thresholds for APP_SEL1:0=10 or APP_SEL1:0=11. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8 - REF_SYNC Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15 - Mode Switching in Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16 - Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 18 - Examples of REF & REF_SYNC to Output Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 19 - Recommended Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 20 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 21 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 22 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 23 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 24 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 25 - REF_SYNC0/1 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 26 - E1 Output Timing Referenced to F8/F32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 27 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 28 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 29 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 Zarlink Semiconductor Inc. ZL30106 1.0 Change Summary Data Sheet Changes from June 2004 Issue to October 2004 Issue. Page, section, figure and table numbers refer to this issue. Page 1 7 18 33 34 34 Item Text Figure 2 Section 3.3 Section 6.4 Table "Absolute Maximum Ratings*" Table "DC Electrical Characteristics*" Change Jitter changed to 24 ps from 20 ps Added note specifying not e-Pad Changed 200 ns to 20 ns in "HMS=0" section Corrected time-constant of example reset circuit Corrected package power rating Corrected current consumption Corrected Schmitt trigger Vt- levels Corrected output voltage note to reflect two pad strengths Updated Min. Max. values 37 Table "AC Electrical Characteristics* Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 24)." Section 7.1 Section 7.2 38 42 Corrected pulse widths Changed jitter numbers 6 Zarlink Semiconductor Inc. ZL30106 2.0 2.1 Data Sheet Physical Description Pin Connections F4/F65o F16o AGND IC REF_SEL0 REF_SEL1 REF0 REF_SYNC0 REF1 REF_SYNC1 REF2 APP_SEL0 VDD NC TIE_CLR BW_SEL 48 50 F8/F32o C16o C2o AVDD AVDD C8/C32o C4/C65o AGND AGND C19o F2ko AVDD AVDD AVCORE AGND AGND 46 44 42 40 38 36 34 32 30 52 28 54 26 56 58 22 60 20 62 18 64 2 4 6 8 10 12 14 16 ZL30106 24 C1.5o C3o C6/8.4/34/44o AVDD OUT_SEL0 OUT_SEL1 OUT_SEL2 VDD APP_SEL1 GND IC OSCi OSCo RST MODE_SEL1 MODE_SEL0 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30106 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30106 does not use the e-Pad TQFP. GND VCORE LOCK HOLDOVER REF_FAIL0 REF_FAIL1 REF_FAIL2 TDO TMS TRST TCK VCORE GND AVCORE TDI HMS 7 Zarlink Semiconductor Inc. ZL30106 2.2 Pin Description Name GND VCORE LOCK HOLDOVER REF_FAIL0 Ground. 0 V Positive Supply Voltage. +1.8 VDC nominal Description Data Sheet Pin # 1 2 3 4 5 Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected input reference. Holdover (Output). This output goes to a logic high whenever the PLL goes into holdover mode. Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0 reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that it is exhibiting abrupt phase or frequency changes. Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1 reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that it is exhibiting abrupt phase or frequency changes. Reference 2 Failure Indicator (Output). A logic high at this pin indicates that the REF2 reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that it is exhibiting abrupt phase or frequency changes. Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. Positive Supply Voltage. +1.8 VDC nominal Ground. 0 V Positive Analog Supply Voltage. +1.8 VDC nominal Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Hitless Mode Switching (Input). The HMS input controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. A logic low at this pin will cause the ZL30106 to maintain the delay stored in the TIE corrector circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high on this pin will cause the ZL30106 to measure a new delay for its TIE corrector circuit thereby minimizing the output phase movement when it transitions from Holdover or Freerun mode to Normal mode. 6 REF_FAIL1 7 REF_FAIL2 8 9 TDO TMS 10 TRST 11 12 13 14 15 TCK VCORE GND AVCORE TDI 16 HMS 17 18 MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode of operation, see Table 4 on page 21. MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description. 8 Zarlink Semiconductor Inc. ZL30106 Pin # 19 Name RST Description Data Sheet Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. When the RST pin goes high, the device will transition into a Reset state for 3 ms. In the Reset state all outputs will be forced into high impedance. Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clock oscillator operation, this pin must be left unconnected. Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to a clock source. Internal Connection. Leave unconnected. Ground. 0 V Application Selection 1 (Input). This input combined with APP_SEL0 selects the application that the ZL30106 is optimized for, see Table 1 on page 20. Positive Supply Voltage. +3.3 VDC nominal Output Selection 2 (Input). This input selects the signals on the combined output clock and frame pulse pins, see Table 3 on page 21. Output Selection 1 (Input). This input combined with OUT_SEL0 selects the signals on the combined output clock pin C6/8.4/34/44o, see Table 3 on page 21. Output Selection 0 (Input). See OUT_SEL1 description. Positive Analog Supply Voltage. +3.3 VDC nominal 20 OSCo 21 OSCi 22 23 24 25 26 27 28 29 30 IC GND APP_SEL1 VDD OUT_SEL2 OUT_SEL1 OUT_SEL0 AVDD C6/8.4/34/44o Clock 6.312 MHz, 8.448 MHz, 34.368 MHz or 44.736 MHz (Output). This output is used in DS2, E2, E3 or DS3 applications. The output frequency is selected via the OUT_SEL1 and OUT_SEL0 pins, see Table 3 on page 21. C3o C1.5o Clock 3.088 MHz (Output). This output is used in DS1 applications. Clock 1.544 MHz (Output). This output is used in DS1 applications. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 31 32 33 34 35 36 37 38 39 40 41 AGND AGND AVCORE AVDD AVDD F2ko C19o AGND AGND Analog Ground. 0 V Analog Ground. 0 V Positive Analog Supply Voltage. +1.8 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Multi Frame Pulse (Output). This is a 2 kHz 51 ns active high framing pulse, which marks the beginning of a multi frame. Clock 19.44 MHz (Output). This output is used in SONET/SDH applications. Analog Ground. 0 V Analog Ground. 0 V 9 Zarlink Semiconductor Inc. ZL30106 Pin # 42 Name C4/C65o Description Data Sheet Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency is selected via the OUT_SEL2 pin, see Table 3 on page 21. Clock 8.192 MHz or 32.768 MHz (Output). This output is used for ST-BUS and GCI operation at 8.192 Mb/s or for operation with a 32.768 MHz clock. The output frequency is selected via the OUT_SEL2 pin, see Table 3 on page 21. In C8 mode, this clock output pad uses an included Schmitt input as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 43 C8/C32o 44 45 46 AVDD AVDD C2o Positive Analog Supply Voltage. +3.3 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Clock 2.048 MHz (Output). This output is used for standard E1 interface timing and for ST-BUS operation at 2.048 Mbit/s. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 47 C16o Clock 16.384 MHz (Output). This output is used for ST-BUS operation with a 16.384 MHz clock. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 48 F8/F32o Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse or it is an 8 kHz 31 ns active high framing pulse, which marks the beginning of a frame. The pulse width is selected via the OUT_SEL2 pin, see Table 3 on page 21. Frame Pulse ST-BUS 2.048 Mbit/s or ST-BUS at 65.536 MHz clock (Output). This output is an 8 kHz 244 ns active low framing pulse which marks the beginning of an STBUS frame. This is typically used for ST-BUS operation at 2.048 Mbit/s and 4.096 Mbit/s. Or this output is an 8 kHz 15 ns active low framing pulse, typically used for ST-BUS operation with a clock rate of 65.536 MHz. The pulse width is selected via the OUT_SEL2 pin, see Table 3 on page 21. Frame Pulse ST-BUS 8.192 Mbit/s (Output). This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 8.192 Mbit/s. Analog Ground. 0 V Internal Connection. Connect this pin to ground. Reference Select 0 (Input/Output). In the manual mode of operation, REF_SEL0 is an input. As an input REF_SEL0 combined with REF_SEL1 selects the reference input that is used for synchronization, see Table 5 on page 23. In the Automatic mode of operation, REFSEL0 is an output indicating which of the input references is the being selected, see Table 6 on page 25. This pin is internally pulled down to GND. Reference Select 1 (Input/Output). See REF_SEL0 pin description. 49 F4/F65o 50 F16o 51 52 53 AGND IC REF_SEL0 54 REF_SEL1 10 Zarlink Semiconductor Inc. ZL30106 Pin # 55 Name REF0 Description Data Sheet Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. This pin is internally pulled down to GND. REF Synchronization Frame Pulse 0 (Input). This is the 2 kHz or 8 kHz (multi) frame pulse synchronization input associated with the REF0 reference. While the PLL is locked to the REF0 input reference the output (multi) frame pulses are synchronized to this input. This pin is internally pulled down to GND. Reference (Input). See REF0 pin description. REF Synchronization Frame Pulse 1 (Input). This is the 2 kHz or 8 kHz (multi) frame pulse synchronization input associated with the REF1 reference. While the PLL is locked to the REF1 input reference the output (multi) frame pulses are synchronized to this input. This pin is internally pulled down to GND. Reference (Input). See REF0 pin description. Application Selection (Input). See APP_SEL1 pin description. Positive Supply Voltage. +3.3 VDC nominal No internal bonding Connection. Leave unconnected. TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase. Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loop filter, see Table 2 on page 20. 56 REF_SYNC0 57 58 REF1 REF_SYNC1 59 60 61 62 63 64 REF2 APP_SEL0 VDD NC TIE_CLR BW_SEL 11 Zarlink Semiconductor Inc. ZL30106 3.0 Functional Description Data Sheet The ZL30106 is a SONET/SDH Network Interface DPLL, providing timing (clock) and synchronization (frame) signals to SONET/SDH and PDH network interface cards. The ZL30106 supports the following applications: * * * * DS1/E1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E Derived DS1 compliant with ITU-T G.783 DS2/DS3/E2/E3 compliant with ANSI T1.102 and ITU-T G.823 SONET/SDH compliant with ITU-T G.813 option 1 and Telcordia GR-253-CORE Figure 1 is a functional block diagram which is described in the following sections. 3.1 Reference Select Multiplexer (MUX) The ZL30106 accepts three simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal, is selected as input to the TIE Corrector Circuit based on the reference selection (REF_SEL1:0) inputs. REF0 and REF1 can be accompanied by a 2 kHz or 8 kHz frame pulse on the REF_SYNC0 and REF_SYNC1 inputs. Input REF_SYNC0 is always associated with input REF0 while input REF_SYNC1 is always associated with input REF1. The use of the combined REF and REF_SYNC inputs allows for a very accurate phase alignment of the output frame pulses to the 2 kHz or 8 kHz (multi) frame pulse supplied to the REF_SYNC input. This feature supports the implementation of line card clocks where the line card locks to the backplane clock with a filter suitable for good tracking (high bandwidth) yet still provides a (multi) frame locked to the backplane (multi) frame. 3.2 Reference Monitor The input references are monitored by three independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. * Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL. Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock is within the selected accuracy range, see Table 1. Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. * * * 12 Zarlink Semiconductor Inc. ZL30106 Data Sheet Reference Frequency Detector OR REF_FAIL0 / REF_FAIL1 / REF_FAIL2 REF0 / REF1 / REF2 Precise Frequency Monitor OR REF_OOR Reference select state machine REF_SEL1:0 Coarse Frequency Monitor dis/re-qualify timer Single Cycle Monitor OR REF_DIS Mode select state machine REF_OOR = reference out of range. REF_DIS= reference disrupted. Both are internal signals. HOLDOVER Figure 3 - Reference Monitor Circuit Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for more than 50 ms. The single cycle and coarse frequency failures must be absent for 200 ms to let the timer re-qualify the input reference signal as valid. Multiple failures of less than 50 ms each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4 where REF0 experiences disruptions while REF1 is stable. SCM or CFM failure SCM or CFM failure REF0 dis/requalify timer on REF0 50 ms REF_OOR0 (internal signal) REF_FAIL0 200 ms HOLDOVER REF_SEL REF0 REF1 REF0 REF1 Figure 4 - Behaviour of the Dis/Re-qualify Timer 13 Zarlink Semiconductor Inc. ZL30106 Data Sheet When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. If the device is set to Automatic mode (MODE_SEL1:0=11), then the state machine does not immediately switch to another reference. If the single cycle and/or coarse frequency failures persist for more than 50 ms or the precise frequency monitor detects a failure, then the state machine will switch to another valid reference if that is available. If there no other reference available, it stays in Holdover mode. The precise frequency monitor's failure thresholds are selected with the APP_SEL pins based on the ZL30106 applications. Figure 5, Figure 6 and Figure 7 show the out of range limits for various master clock accuracies. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference. C20i Clock Accuracy C20 0 ppm -83 -64 0 64 83 Out of Range In Range C20 +32 ppm -51 -32 32 96 115 Out of Range In Range C20 -32 ppm -115 -96 -32 32 51 Out of Range In Range -100 C20: 20 MHz master oscillator clock -75 -50 -25 0 25 50 75 100 Frequency offset [ppm] Figure 5 - Out-of-Range Thresholds for APP_SEL1:0=00 C20i Clock Accuracy C20 0 ppm -12 -9.2 0 9.2 12 Out of Range In Range C20 +4.6 ppm -7.4 -4.6 4.6 13.8 16.6 Out of Range In Range C20 -4.6 ppm -16.6 -13.8 -4.6 4.6 7.4 Out of Range In Range C20: 20 MHz master oscillator clock -15 -10 -5 0 5 10 15 Frequency offset [ppm] Figure 6 - Out-of-Range Thresholds for APP_SEL1:0=01 14 Zarlink Semiconductor Inc. ZL30106 Data Sheet C20i Clock Accuracy C20 0 ppm -52 -40 0 40 52 Out of Range In Range C20 +20 ppm -32 -20 20 60 72 Out of Range In Range C20 -20 ppm -72 -60 -32 20 32 Out of Range In Range -100 C20: 20 MHz master oscillator clock -75 -50 -25 0 25 50 75 100 Frequency offset [ppm] Figure 7 - Out-of-Range Thresholds for APP_SEL1:0=10 or APP_SEL1:0=11 . In addition to the monitoring of the REF reference signals the companion REF_SYNC input signals are also monitored for failure (see Figure 8). * REF_SYNC Frequency Detector (RSFD): This detector determines whether the frequency of the REF_SYNC frame pulse is 2 kHz or 8 kHz and provides this information to the REF/SYNC ratio monitor circuits and the phase detector circuit of the DPLL. REF_SYNC Ratio Monitor (RSRM): This monitor checks the number of REF reference clock cycles in a single associated REF_SYNC frame pulse period to determine the integrity of the REF_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF reference clock in a single 8 kHz REF_SYNC frame pulse period to validate the REF_SYNC signal. If the REF and REF_SYNC inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL will abandon the mechanism of aligning the output frame pulse to the REF_SYNC pulse. Instead only the REF reference will be used for synchronization. * REF_SYNC REF REF frequency REF_SYNC Ratio Monitor to DPLL REF_SYNC frequency REF_SYNC Frequency Detector Figure 8 - REF_SYNC Monitor Circuit 15 Zarlink Semiconductor Inc. ZL30106 3.3 Time Interval Error (TIE) Corrector Circuit Data Sheet The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the recovery from Holdover mode to Normal mode. On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it recovers from Holdover mode. The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown in Figure 24. The speed of the phase alignment correction is limited by the loop filter bandwidth. Convergence is always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case the output clocks will always align with the selected input reference. This is illustrated in Figure 9. TIE_CLR = 0 locked to REF0 REF0 REF0 TIE_CLR = 1 locked to REF0 REF1 REF1 Output Clock Output Clock locked to REF1 REF0 REF0 locked to REF1 REF1 REF1 Output Clock Output Clock Figure 9 - Timing Diagram of Hitless Reference Switching The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode (see Figure 10). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode. This causes accumulation of phase in network elements. In both cases the PLL's output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30106 is always hitless unless TIE_CLR is kept low continuously. 16 Zarlink Semiconductor Inc. ZL30106 HMS = 0 Normal mode REF REF Data Sheet HMS = 1 Normal mode Output Clock Output Clock Phase drift in Holdover mode REF REF Phase drift in Holdover mode Output Clock Output Clock Return to Normal mode REF REF Return to Normal mode Output Clock Output Clock TIE_CLR=0 REF REF TIE_CLR=0 Output Clock Output Clock Figure 10 - Timing Diagram of Hitless Mode Switching Examples: HMS=1: When ten Normal to Holdover to Normal mode transitions occur and in each case the Holdover mode was entered for 2 seconds then the accumulated phase change (MTIE) could be as large as 330 ns. Phaseholdover_drift = 0.01 ppm x 2 s = 20 ns Phasemode_change = 0 ns + 13 ns = 13 ns Phase10 changes = 10 x (20 ns + 13 ns) = 330 ns 17 Zarlink Semiconductor Inc. ZL30106 where: 0.01 ppm is the accuracy of the Holdover mode Data Sheet 0 ns is the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode 13 ns is the maximum phase discontinuity in the transition from the Holdover mode to the Normal mode when a new TIE corrector value is calculated HMS=0: When the same ten Normal to Holdover to Normal mode changes occur and in each case Holdover mode was entered for 2 seconds, then the overall MTIE would be 20 ns. As the delay value for the TIE corrector circuit is not updated, there is no 13 ns measurement error at this point. The phase can still drift for 20 ns when the PLL is in Holdover mode but when the PLL enters Normal mode again, the phase moves back to the original point so the phase is not accumulated. 3.4 Digital Phase Lock Loop (DPLL) The DPLL of the ZL30106 consists of a phase detector, a limiter, a loop filter and a digitally controlled oscillator as shown in Figure 11. The data path from the phase detector to the limiter is tapped and routed to the lock detector that provides a lock indication which is output at the LOCK pin. Lock Detector Virtual Reference from TIE Corrector Circuit LOCK Phase Detector REF_SYNC frame pulse Limiter Loop Filter Digitally Controlled Oscillator DPLL Reference to Frequency Synthesizer State Select from Control State Machine Feedback signal from Frequency Select MUX Feedback frame pulse; F8o or F2ko Figure 11 - DPLL Block Diagram Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the feedback signal and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the limiter circuit. Limiter - the limiter receives the error signal from the phase detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope compliant with the applicable standards. The phase slope limit is dependent on the APP_SEL1:0 and BW_SEL pins and is listed in Table 2. Loop Filter - the loop filter is similar to a first order low pass filter with a bandwidth selected by the BW_SEL pin, suitable to provide timing and synchronization for SONET/SDH and PDH network interface cards. For stability reasons, the loop filter bandwidth for 2 kHz references is always 14 Hz and the loop filter bandwidth for 8 kHz references is limited to a maximum of 58 Hz. 18 Zarlink Semiconductor Inc. ZL30106 Data Sheet Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30106. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in Normal Mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before the ZL30106 entered Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the holdover frequency. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source. Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lockwindow for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into Holdover mode (auto or manual), the LOCK pin will initially stay high for 0.1 s. If at that point the DPLL is still in holdover mode, the LOCK pin will go low. In Freerun mode the LOCK pin will go low immediately. 3.5 Frequency Synthesizers The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance loads. 3.6 State Machine As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30106 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS. 3.7 Master Clock The ZL30106 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. 19 Zarlink Semiconductor Inc. ZL30106 4.0 4.1 Data Sheet Control and Modes of Operation Application Selection Table 1 lists the applications that are supported by the ZL30106 with the corresponding frequency out of range limits. APP_SEL 00 01 10 11 Application DS1/E1 Derived DS1 DS2/E2/DS3/E3 SONET/SDH Applicable Standard ANSI T1.403 Telcordia GR-1244-CORE Stratum 4/4E ITU-T G.783 ANSI T1.102 ITU-T G.823 ITU-T G.813 Option 1 Telcordia GR-253-CORE Out Of Range Limits 64 - 83 ppm 9.6 - 12 ppm 40 - 52 ppm 40 - 52 ppm Table 1 - Application Selection and the Out of Range Limits 4.2 Loop Filter and Limiter Selection The loop filter and limiter settings are selected through the APP_SEL and BW_SEL pins, see Table 2. The maximum loop filter bandwidth is also dependent on the frequency of the currently selected reference (REF0/1/2). APP_SEL1:0 BW_SEL Detected REF Frequency 2 kHz Loop Filter Bandwidth 14 Hz 29 Hz Phase Slope Limiting 61 s/s 00 or 10 (DS1/E1 or DS2/E2/DS3/E3) 0 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz 2 kHz 14 Hz 29 Hz 9.5 ms /s 01 (Derived DS1) 0 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz 2 kHz 14 Hz 29 Hz 7.5 s/s 11 (SONET/SDH) 0 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz 2 kHz 8 kHz 14 Hz 58 Hz 922 Hz 9.5 ms /s 00, 01, 10 or 11 (all applications) 1 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz Table 2 - Loop Filter and Limiter Settings 20 Zarlink Semiconductor Inc. ZL30106 4.3 Output Clock and Frame Pulse Selection Data Sheet The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). These signals are available in two groups controlled by the OUT_SEL2:0 pins, see Table 3. OUT_SEL2 0 1 OUT_SEL1:0 00 01 10 11 C6o C8.4o C34o C44o Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin Generated Clocks C2o, C4o, C8o, C16o C2o, C16o, C32, C65o Generated Frame Pulses F4o, F8o, F16o F16o, F32o, F65o 4.4 Modes of Operation The ZL30106 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are selected with mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one mode to the other is controlled by an external controller. The ZL30106 can be configured to automatically select a valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of operation, a state machine controls selection of references (REF0 or REF1) used for synchronization. MODE_SEL1 0 0 1 1 MODE_SEL0 0 1 0 1 Mode Normal (with automatic Holdover) Holdover Freerun Automatic (Normal with automatic Holdover and automatic reference switching) Table 4 - Operating Modes 4.4.1 Freerun Mode Freerun mode is typically used when an independent clock source is required or immediately following system power-up before network synchronization is achieved. In Freerun mode, the ZL30106 provides timing and synchronization signals which are based on the master clock frequency (supplied to OSCi pin) only and are not synchronized to the reference input signals. The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32 ppm output clock is required, the master clock must also be 32 ppm. See Applications - Section 6.2, "Master Clock". 21 Zarlink Semiconductor Inc. ZL30106 4.4.2 Holdover Mode Data Sheet Holdover Mode is typically used for short durations while system synchronization is temporarily disrupted. In Holdover Mode, the ZL30106 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30106 output reference frequency is stored alternately in two memory locations every 26 ms. When the device is switched into Holdover Mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.01 ppm. Two factors affect the accuracy of Holdover mode. One is drift on the master clock while in Holdover mode, drift on the master clock directly affects the Holdover mode accuracy. Note that the absolute master clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a 32 ppm master clock may have a temperature coefficient of 0.1 ppm per C. So a 10 C change in temperature, while the ZL30106 is in Holdover mode may result in an additional offset (over the 0.01 ppm) in frequency accuracy of 1 ppm. Which is much greater than the 0.01 ppm of the ZL30106. The other factor affecting the accuracy is large jitter on the reference input prior to the mode switch. 4.4.3 Normal Mode Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal mode, the ZL30106 provides timing and frame synchronization signals, which are synchronized to one of three reference inputs (REF0, REF1 or REF2). The input reference signal may have a nominal frequency of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. The frequency of the reference inputs are automatically detected by the reference monitors. When the ZL30106 comes out of RESET while Normal mode is selected by its MODE_SEL pins then it will initially go into Holdover mode and generate clocks with the accuracy of its freerunning local oscillator (see Figure 12). If the ZL30106 determines that its selected reference is disrupted (see Figure 3), it will remain in Holdover until the selected reference is no longer disrupted or the external controller selects another reference that is not disrupted. If the ZL30106 determines that its selected reference is not disrupted (see Figure 3) then the state machine will cause the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin. If HMS=0 then the ZL30106 will transition directly to Normal mode and it will align its output signals with its selected input reference (see Figure 10). If HMS=1 then the ZL30106 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the selected input reference will be maintained. When the ZL30106 is operating in Normal mode, if it determines that its selected reference is disrupted (Figure 3) then its state machine will cause it to automatically go to Holdover mode. When the ZL30106 determines that its selected reference is not disrupted then the state machine will cause the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 12). If HMS=0 then the ZL30106 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 10). If HMS=1 then the ZL30106 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained. If the reference selection changes because the value of the REF_SEL1:0 pins changes or because the reference selection state machine selected a different reference input, the ZL30106 goes into Holdover mode and returns to Normal mode through the TIE correction state regardless of the logic value on HMS pin. 22 Zarlink Semiconductor Inc. ZL30106 Data Sheet Normal (HOLDOVER=0) REF_CH=1 and (REF_SYNC failed) REF_DIS=0 REF_DIS=1 REF_DIS=1 Holdover (HOLDOVER=1) (REF_DIS=0 and HMS=1) or REF_CH=1 TIE Correction (HOLDOVER=1) RST REF_DIS=0 and REF_CH=0 and HMS=0 REF_DIS=1: Current selected reference disrupted (see Figure 3) REF_CH= 1: Reference change, a transition in the reference selection (see Figure 14) or a change in the REF_SEL pins. Figure 12 - Mode Switching in Normal Mode 4.4.4 Automatic Mode The Automatic mode combines the functionality of the Normal mode (automatic Holdover) with automatic reference switching. The automatic reference switching is described in more detail in section 4.5.2, "Automatic Reference Switching". 4.5 4.5.1 Reference Switching Manual Reference Switching In the manual modes of operation (MODE_SEL1:0 11) the active reference input (REF0, REF1 or REF2) is selected by the REF_SEL1 and REF_SEL0 pins as shown in Table 5. When the logic value of the REF_SEL pins is changed when the DPLL is in Normal mode, the ZL30106 will perform a hitless reference switch. REF_SEL1 0 0 1 1 REF_SEL0 0 1 0 1 Input Reference Selected REF0 REF1 REF2 REF2 Table 5 - Manual Reference Selection When the REF_SEL inputs are used in Normal mode to force a change from the currently selected reference to another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process. 23 Zarlink Semiconductor Inc. ZL30106 Data Sheet REF_SEL REF0 REF1 LOCK Lock Time Note: LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 13 - Reference Switching in Normal Mode 4.5.2 Automatic Reference Switching In the automatic mode of operation (MODE_SEL1:0 = 11), the ZL30106 automatically selects a reference input that is not out-of-range (REF_OOR=0, see Figure 3). The state machine can only select REF0 or REF1. REF2 cannot be selected in the Automatic mode. See Figure 14. If the current reference (REF0 or REF1) used for synchronization fails, the state machine will switch to the other reference. If both references fail then the ZL30106 enters the Holdover mode without switching to another reference. When the ZL30106 comes out of reset or when REF2 is the current reference when the ZL30106 is put in the Automatic mode, then REF0 has priority over REF1. Otherwise there is no preference for REF0 or REF1 which is referred to as non-revertive reference selection. RST && REF_OOR0=0 RST && REF_OOR0=1 && REF_OOR1=0 REF_OOR0=0 && REF_OOR1=1 REF0 Reference REF_OOR0=1 && REF_OOR1=0 REF_OOR0=0 REF_OOR0=1 && REF_OOR1=0 REF1 Reference REF2 Reference REF_OOR = reference out of range, see Figure 3 Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11) 24 Zarlink Semiconductor Inc. ZL30106 Data Sheet In the automatic mode of operation, both pins REF_SEL1 and REF_SEL0 are configured as outputs. The logic level on the REF_SEL0 output indicates the current input reference being selected for synchronization (see Table 6). REF_SEL1 (output pin) 0 0 REF_SEL0 (output pin) 0 1 Input Reference REF0 REF1 Table 6 - The Reference Selection Pins in the Automatic Mode The mode selection state machine behaves differently in Automatic mode in that when both reference REF0 and reference REF1 are out of range (REF_OOR=1), the state machine will select the Holdover state. In Normal mode the reference out of range (REF_OOR) status is ignored by the state machine. This is illustrated in Figure 15. Normal (HOLDOVER=0) REF_DIS=0 and REF_OOR=0 and REF_CH=0 and HMS=0 RST REF_DIS=1 or REF_OOR=1 Holdover (HOLDOVER=1) TIE Correction (HOLDOVER=1) REF_CH=1 REF_DIS=0 and REF_OOR=0 (REF_DIS=0 and REF_OOR=0 and HMS=1) or REF_CH=1 REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal. REF_OOR=1: Current selected reference out of range (see Figure 3). REF_OOR is an internal signal. REF_CH= 1: Reference change, a transition in the reference selection (see Figure 14). REF_CH is an internal signal. Figure 15 - Mode Switching in Automatic Mode 4.5.2.1 Automatic Reference Switching - Coarse Reference Failure When the currently-active input reference in Automatic mode fails in a coarse manner, the REF_DIS internal signal places the device in holdover, with the HOLDOVER pin and the REF_FAIL pin asserted. This can occur through triggering the Single Cycle Monitor, or the Coarse Frequency Monitor, in the Reference Monitor block. If the reference does not correct itself within the reference-disqualify duration (50 milliseconds) the HOLDOVER pin is deasserted and the REF_SEL outputs indicate that the device has switched to the other reference. Where the new reference is close enough in frequency and TIE-corrected phase for the output to stay within the phase-lockwindow, the LOCK output will remain asserted through the reference-switch process. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 16 illustrates this process. If the reference corrects itself within the reference-disqualify duration (< 50 milliseconds) the HOLDOVER pin is deasserted, the REF_FAIL pin is de-asserted, and the REF_SEL outputs indicate that the device has remained locked to the old reference. The LOCK pin remains asserted. 25 Zarlink Semiconductor Inc. ZL30106 SCM or CFM failure Data Sheet REF0 REF_DIS0 (internal signal) 50 ms REF_OOR0 (internal signal) REF_FAIL0 10 s HOLDOVER REF_SEL REF0 REF1 LOCK Lock Time Note: This scenario is based on REF1 remaining good throughout the duration. LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 16 - Automatic Reference Switching - Coarse Reference Failure 4.5.2.2 Automatic Reference Switching - Reference Frequency Out-of-Range When the currently-active input reference in Automatic mode fails through a subtle frequency offset, the REF_FAIL output is asserted as soon as the Precise Frequency Monitor indicates an out-of-range reference (10 to 20 seconds). The HOLDOVER output is briefly asserted (approximately three reference input cycles) and the REF_SEL outputs indicate that the device has switched to the other reference. Where the new reference is close enough in frequency and TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will deassert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 17 illustrates this process. 26 Zarlink Semiconductor Inc. ZL30106 Frequency Precision failure Data Sheet REF0 10 to 20 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1 LOCK Lock Time Note: This scenario is based on REF1 remaining good throughout the duration. LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure 4.6 Clock-and-Sync Pair Synchronization The ZL30106 can lock directly to a 2 kHz reference or an 8 kHz reference, but the low frequency of these references restricts the value of the highest loop filter that can be used. The clock-and-sync pair synchronization technique enables the ZL30106 to align its output 2 kHz and 8 kHz frame pulses with 2 kHz and 8 kHz references without restricting the loop filter. Therefore the output clocks and frame pulses will track the input clock and frame pulse pair closely even in the presence of jitter on the reference input. The clock-and-sync pair mechanism is enabled as soon as a valid 2 kHz or 8 kHz frame pulse is detected on the REF_SYNC input. The REF_SYNC pulse must be generated from the clock that is present on the REF input. The ZL30106 checks the number of REF cycles in the REF_SYNC period. If this is not the nominal number of cycles, the REF_SYNC pulse is considered invalid. For example, if REF is a 8.192 MHz clock then there must be exactly 1024 REF cycles in a REF_SYNC period. If a valid REF_SYNC pulse is detected, the ZL30106 will align the rising edges of the REF clock and the corresponding output clock such that the rising edge of the F2ko or F8o/F32o output frame pulse is aligned with the frame boundary indicated by the REF_SYNC signal. The rising edges of the REF and the corresponding output clock that are aligned, are the ones that lag the rising edges of the REF_SYNC and the F8o pulses respectively. This is illustrated in Figure 18. If an ST_BUS clock and frame pulse pair is used as the REF and REF_SYNC inputs, the ST-BUS frame pulse must be inverted first before it can be used as the REF_SYNC pulse. If a clock and frame pulse pair is used for synchronization, the TIE correction value should be cleared by keeping the TIE_CLR pin low for at least 15 ns. Otherwise a static phase offset may remain between the output frame pulse and the REF_SYNC frame pulse. Reference switching from one REF- REF_SYNC pair to the other REFREF_SYNC pair does not activate the TIE correction circuit and the ZL30106 will align the output frame pulse to the new REF_SYNC frame pulse. In that case the MTIE can be as large as 250 s for a 2 kHz REF_SYNC signal and 27 Zarlink Semiconductor Inc. ZL30106 Data Sheet 62.5 s for an 8 kHz REF_SYNC signal. Reference switching from a REF- REF_SYNC pair to a single REF input however, is hitless unless the TIE_CLR pin is kept low. If a REF - REF_SYNC pair is used as the reference then if the ZL30106 transitions from Holdover to Normal mode, the TIE correction circuit will not be activated and the PLL will align its output clock and frame pulse with the input REF and REF_SYNC pair. REF_SYNC0/1 = 8 kHz REF0/1 = C8o aligned F8o C8o REF_SYNC0/1 = 2 kHz REF0/1 = C19o aligned F2ko C19o Figure 18 - Examples of REF & REF_SYNC to Output Alignment 28 Zarlink Semiconductor Inc. ZL30106 5.0 Measures of Performance Data Sheet The following are some PLL performance indicators and their corresponding definitions. 5.1 Jitter Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or 20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 5.2 Jitter Generation (Intrinsic Jitter) Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Jitter is usually measured with various bandlimiting filters depending on the applicable standards. 5.3 Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. 5.4 Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the Zarlink digital PLLs two internal elements determine the jitter attenuation; the internal low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to, for example, 61 s/s. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated). Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (for example 75% of the specified maximum tolerable input jitter). 5.5 Frequency Accuracy The Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. 5.6 Holdover Accuracy Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30106, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. 29 Zarlink Semiconductor Inc. ZL30106 5.7 Pull-in Range Data Sheet Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into synchronization. 5.8 Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. 5.9 Phase Slope Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Another way of specifying the phase slope is as the fractional change per time unit. For example; a phase slope of 61 s/s can also be specified as 61 ppm. 5.10 Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. 5.11 Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. 5.12 Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. 5.13 Lock Time This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: * * * * * initial input to output phase difference initial input to output frequency difference PLL loop filter bandwidth PLL phase slope limiter in-lock phase distance The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. 30 Zarlink Semiconductor Inc. ZL30106 6.0 Applications Data Sheet This section contains ZL30106 application specific details for power supply decoupling, reset operation, clock and crystal operation. 6.1 Power Supply Decoupling It is recommended to place a 100 nF decoupling capacitor close to each pair of power and ground pins as illustrated in Figure 19 to ensure optimal jitter performance. 3.3 V 29 AV DD 100 nF 33 AGND 44 AV DD 100 nF 41 AGND 45 AV DD 100 nF 51 AGND 37 AV DD 100 nF 40 GND 36 AVDD 100 nF 34 GND 25 V DD 100 nF 23 GND 61 V DD 100 nF 1 GND V CORE 12 100 nF GND 13 V CORE 2 100 nF GND 1 AV CORE 14 100 nF AV CORE 35 100 nF 1.8 V ZL30106 Figure 19 - Recommended Power Supply Decoupling 6.2 Master Clock The ZL30106 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30106. 6.2.1 Clock Oscillator When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30106, and the OSCo output should be left open as shown in Figure 20. 31 Zarlink Semiconductor Inc. ZL30106 1 2 3 4 Frequency Tolerance Rise & fall time Duty cycle 20 MHz as required < 10 ns 40% to 60% Data Sheet Table 7 - Typical Clock Oscillator Specification ZL30106 OSCi +3.3 V +3.3 V 20 MHz OUT GND 0.1 F OSCo No Connection Figure 20 - Clock Oscillator Circuit 6.2.2 Crystal Oscillator Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 21. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. A typical crystal oscillator specification and circuit is shown in Table 8 and Figure 21 respectively. . 1 2 3 4 5 6 Frequency Tolerance Oscillation mode Resonance mode Load capacitance Maximum series resistance 20 MHz as required fundamental parallel as required 50 Table 8 - Typical Crystal Oscillator Specification 32 Zarlink Semiconductor Inc. ZL30106 20 MHz OSCi Data Sheet ZL30106 1 M OSCo 100 1 H The 100 resistor and the 1 H inductor may improve stability and are optional. Figure 21 - Crystal Oscillator Circuit 6.3 Power Up Sequence The ZL30106 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power-up the 3.3 V supply fully first, then power up the 1.8 V supply 2. Power up the 3.3 V supply and the 1.8 V supply simultaneously, ensuring that the 3.3 V supply is never lower than a few hundred millivolts below the 1.8 V supply (e.g., by using a schottky diode or controlled slew rate) 6.4 Reset Circuit A simple power up reset circuit with about a 60 s reset low time is shown in Figure 22. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30106 +3.3 V R 10 k RST RP 1 k C 10 nF Figure 22 - Power-Up Reset Circuit 33 Zarlink Semiconductor Inc. ZL30106 7.0 7.1 Data Sheet Characteristics AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 8 Supply voltage Core supply voltage Voltage on any digital pin Voltage on OSCi and OSCo pin Current on any pin Storage temperature TQFP 64 pin package power dissipation ESD rating Symbol VDD_R VCORE_R VPIN VOSC IPIN TST PPD VESD -55 Min. -0.5 -0.5 -0.5 -0.3 Max. 4.6 2.5 6 VDD + 0.3 30 125 500 2 Units V V V V mA C mW kV * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated. Recommended Operating Conditions* Characteristics 1 2 3 Supply voltage Core supply voltage Operating temperature Sym. VDD VCORE TA Min. 2.97 1.62 -40 Typ. 3.30 1.80 25 Max. 3.63 1.98 85 Units V V C * Voltages are with respect to ground (GND) unless otherwise stated. DC Electrical Characteristics* Characteristics 1 2 3 4 5 6 7 8 9 Supply current with: OSCi = 0 V OSCi = Clock, OUT_SEL=000 OSCi = Clock, OUT_SEL=111 Core supply current with: OSCi = 0 V OSCi = Clock Schmitt trigger Low to High threshold point Schmitt trigger High to Low threshold point Input leakage current High-level output voltage Sym. IDDS IDD IDD ICORES ICORE Vt+ VtIIL VOH Min. 1 30 45 0 14 1.47 0.8 -105 2.4 Max. 8 60 78 28 20 1.5 1.0 105 Units mA mA mA A mA V V A V VI = VDD or 0 V IOH = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs All device inputs are Schmitt trigger type. outputs loaded with 30 pF Notes 34 Zarlink Semiconductor Inc. ZL30106 DC Electrical Characteristics* Characteristics 10 Low-level output voltage Sym. VOL Min. Max. 0.4 Units V Data Sheet Notes IOL = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 23). Characteristics 1 2 3 Threshold Voltage Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low Sym. VT VHM VLM CMOS 0.5 * VDD 0.7 * VDD 0.3 * VDD Units V V V * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. Timing Reference Points ALL SIGNALS tIRF, tORF tIRF, tORF V HM VT V LM Figure 23 - Timing Parameter Measurement Voltage Levels AC Electrical Characteristics* - Input timing for REF0, REF1 and REF2 references (see Figure 24). Characteristics 1 2 3 4 5 6 7 8 2 kHz reference period 8 kHz reference period 1.544 MHz reference period 2.048 MHz reference period 8.192 MHz reference period 16.384 MHz reference period 19.44 MHz reference period reference pulse width high or low Symbol tREF2kP tREF8kP tREF1.5P tREF2P tREF8P tREF16P tREF8kP tREFW Min. 484 121 338 263 63 38 38 15 Typ. 500 125 648 488 122 61 51 Max. 515 128 950 712 175 75 75 Units s s ns ns ns ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-ofRange limits. 35 Zarlink Semiconductor Inc. ZL30106 Data Sheet tREF output clock with the same frequency as REF tREF tREF8kD, tREF Figure 24 - REF0/1/2 Input Timing and Input to Output Timing AC Electrical Characteristics* - Input timing for REF_SYNC0/1 (see Figure 25). Characteristics 1 2 3 4 5 REF_SYNC0/1 pulse width high or low REF_SYNC0/1 lead time REF_SYNC0/1 lag time REF_SYNC0/1 frequency 2 kHz 8 kHz 2 kHz 8 kHz 2 kHz, 8 kHz Symbol tSYNC_LD tSYNC_LD tSYNC_LG tSYNC_LG tSYNC_W 15 Min. Max. 0 12 tREFP - 15 tREFP - 28 Units ns ns ns ns ns tREFP = minimum period of REF0/1 clock tREFP = minimum period of REF0/1 clock Notes * Supply voltage and operating temperature are as per Recommended Operating Conditions. * See Figure 18, "Examples of REF & REF_SYNC to Output Alignment" on page 28 for further explanation. edge used for alignment tREFP REF0/1 tSYNC_LD tSYNC_LG REF_SYNC0/1 tSYNC_W Note: REF0/1 can be 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. REF_SYNC0/1 can be 2 kHz or 8 kHz. Figure 25 - REF_SYNC0/1 Timing 36 Zarlink Semiconductor Inc. ZL30106 Data Sheet AC Electrical Characteristics* - Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 24). Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 2 kHz reference input to F2ko delay 2 kHz reference input to F8/F32o delay 8 kHz reference input to F8/F32o delay 1.544 MHz reference input to C1.5o delay 1.544 MHz reference input to F8/F32o delay 2.048 MHz reference input to C2o delay 2.048 MHz reference input to F8/F32o delay 8.192 MHz reference input to C8o delay 8.192 MHz reference input to F8/F32o delay 16.384 MHz reference input to C16o delay 16.384 MHz reference input to F8/F32o delay 19.44 MHz reference input to C19o delay 19.44 MHz reference input to F8/F32o delay Symbol tREF2kD tREF2k_F8D tREF8kD tREF1.5D tREF1.5_F8D tREF2D tREF2_F8D tREF8D tREF8_F8D tREF16D tREF16_F8D tREF19D tREF19_F8D Min. 0 -27.2 -0.3 -1.2 -1.1 -1.2 -0.6 -2.0 -1.0 -1.1 29.0 0.2 -1.7 Max. 1.2 -26.5 2.0 0.2 0.9 0 0.8 0.1 1.8 1.9 30.6 1.1 -1.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. 37 Zarlink Semiconductor Inc. ZL30106 AC Electrical Characteristics* - E1 output timing (see Figure 26). Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 C2o delay C2o pulse width low F4o pulse width low F4o delay C4o pulse width low C4o delay F8o pulse width high C8o pulse width low C8o delay F16o pulse with low F16o delay C16o pulse width low C16o delay F32o pulse width high C32o pulse width low C32o delay F65o pulse with low F65o delay C65o pulse width low C65o delay Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC2D tC2L tF4L tF4D tC4L tC4D tF8H tC8L tC8D tF16L tF16D tC16L tC16D tF32H tC32L tC32D tF65L tF65D tC65L tC65D tOR tOF Min. -0.4 243.0 243.3 121.5 121.0 -0.3 121.6 60.3 -0.4 60.3 29.9 28.7 -0.5 30.0 14.7 -0.5 14.7 7.1 7.2 -1.0 1.1 1.2 Max. 0.3 244.1 244.3 122.2 122.4 1.1 123.5 61.3 0.3 61.2 30.8 30.8 1.5 32.1 15.5 0.5 15.5 8.0 8.1 1.0 2.0 2.3 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet Notes outputs loaded with 30 pF * Supply voltage and operating temperature are as per Recommended Operating Conditions. 38 Zarlink Semiconductor Inc. ZL30106 Data Sheet tF8H F8o tC2L C2o tF4L F4o tC4L C4o tC8L C8o tF16D tC2D tF4D tC4D tC8D tF16L F16o tC16L C16o tF32H F32o tC32L C32o tF65D tF65L F65o tC65L C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. tC65D tC32D tC16D Figure 26 - E1 Output Timing Referenced to F8/F32o 39 Zarlink Semiconductor Inc. ZL30106 AC Electrical Characteristics* - DS1 output timing (see Figure 27). Characteristics 1 2 3 4 5 6 C1.5o delay C1.5o pulse width low C3o delay C3o pulse width low Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC1.5D tC1.5L tC3D tC3L tOR tOF Min. -0.6 323.1 -0.7 161.1 1.1 1.2 Max. 0.6 324.0 0.5 162.0 2.0 2.3 Units ns ns ns ns ns ns Data Sheet Notes outputs loaded with 30 pF * Supply voltage and operating temperature are as per Recommended Operating Conditions. o F8_32o tC1.5L tC1.5D C1.5o tC3L tC3D C3o Figure 27 - DS1 Output Timing Referenced to F8/F32o AC Electrical Characteristics* - SDH output timing (see Figure 28). Characteristics 1 2 3 4 5 6 C19o delay C19o pulse width low F2ko delay F2ko pulse width high Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC19D tC19L tF2kD tF2kH tOR tOF Min. -1.0 25.0 25.0 51.1 1.1 1.2 Max. 0.5 25.8 26.6 51.8 2.0 2.3 Units ns ns ns ns ns ns outputs loaded with 30 pF Notes * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o tC19L tC19D C19o tF2D tF2kH F2ko Figure 28 - SDH Output Timing Referenced to F8/F32o 40 Zarlink Semiconductor Inc. ZL30106 AC Electrical Characteristics* - DS2, E2, E3 and DS3 Output Timing (see Figure 29). Characteristics 1 2 3 4 5 6 7 8 9 10 C6o delay C6o pulse width low C8.4o delay C8.4o pulse width low C34o delay C34o pulse width low C44o delay C44o pulse width low Output clock and frame pulse rise time Output clock and frame pulse fall time Sym. tC6D tC6L tC8.4D tC8.4L tC34D tC34L tC44D tC44L tOR tOF Min. -0.70 78.5 -0.8 58.4 -0.5 13.5 -1.0 10.4 1.1 1.2 Max. 0.70 79.3 0.8 59.2 0.5 14.6 0.5 11.2 2.0 2.3 Units ns ns ns ns ns ns ns ns ns ns Data Sheet Notes outputs loaded with 30 pF * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o tC44L tC44D C44o tC34L tC34D C34o tC8.4L C8.4o tC6L C6o tC6D tC8.4D Figure 29 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o 41 Zarlink Semiconductor Inc. ZL30106 AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 2 3 4 5 6 Oscillator Tolerance - DS1/E1 Oscillator Tolerance - Derived DS1 Oscillator Tolerance - DS2/DS3/E2/E3 SONET/SDH Duty cycle Rise time Fall time Min. -32 -4.6 -20 40 Max. +32 +4.6 +20 60 10 10 Units ppm ppm ppm % ns ns Notes Data Sheet * Supply voltage and operating temperature are as per Recommended Operating Conditions. 7.2 Performance Characteristics Performance Characteristics* - Functional Characteristics 1 2 3 4 Holdover accuracy Holdover stability Freerun accuracy Capture Range Reference Out of Range Threshold (including hysteresis) 5 6 7 DS1/E1 (APP_SEL=00) Derived DS1 (APP_SEL=01) DS2/DS3/E2/E3 (APP_SEL=10), SONET/SDH (APP_SEL=11) Lock Time 8 9 10 11 14 Hz filter 29 Hz filter 58 Hz filter 922 Hz filter Output Phase Continuity (MTIE) 12 Reference switching 13 ns TIE_CLR=1 1.5 1 1 1 1.5 1 1 1 s s s s 9.2 to 64 ppm frequency offset 9.2 to 64 ppm frequency offset 9.2 to 64 ppm frequency offset 9.2 to 64 ppm frequency offset -64 -83 -9.2 -12 -40 -52 +64 +83 +9.2 +12 +40 +52 ppm ppm ppm The 20 MHz master clock oscillator set at 0 ppm The 20 MHz master clock oscillator set at 0 ppm The 20 MHz master clock oscillator set at 0 ppm -130 Min. Max. 0.01 0 0 +130 Units ppm ppm ppm ppm Determined by stability of the 20 MHz master clock oscillator Determined by accuracy of the 20 MHz master clock oscillator The 20 MHz master clock oscillator set at 0 ppm Notes 42 Zarlink Semiconductor Inc. ZL30106 Performance Characteristics* - Functional (continued) Characteristics 13 14 Switching from Normal mode to Holdover mode Switching from Holdover mode to Normal mode Output Phase Slope 15 16 17 DS1/E1 (APP_SEL=00), DS2/DS3/E2/E3 (APP_SEL=10) SONET/SDH (APP_SEL=11) Derived DS1 (APP_SEL=01) 61 7.5 9.5 s/s s/s ms/s Min. Max. 0 13 Units ns ns Notes Data Sheet TIE_CLR=1 and HMS=1 * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Input Wander and Jitter Tolerance Conformance Input reference frequency 1 2 3 1.544 MHz 2.048 MHz 19.44 MHz Standard Telcordia GR-1244-CORE ITU-T G.823 ITU-T G.813 Interface DS1 Line timing, DS1 External timing 2048 kbit/s Option 1 * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Output Jitter Generation - ANSI T1.403 conformance ANSI T1.403 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30106 maximum jitter generation Units DS1 Interface 1 2 C1.5o (1.544 MHz) 8 kHz to 40 kHz 10 Hz to 40 kHz 0.07 UIpp 0.5 UIpp 45.3 324 0.30 0.32 nspp nspp * Supply voltage and operating temperature are as per Recommended Operating Conditions. 43 Zarlink Semiconductor Inc. ZL30106 Performance Characteristics*: Output Jitter Generation - ITU-T G.747 conformance ITU-T G.747 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain Data Sheet ZL30106 maximum jitter generation Units DS2 Interface 1 C6o (6.312 MHz) 10 Hz to 60 kHz 0.05 UIpp 7.92 0.20 nspp * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Output Jitter Generation - ITU-T G.812 conformance ITU-T G.812 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30106 maximum jitter generation Units E1 Interface 1 C2o (2.048 MHz) 20 Hz to 100 kHz 0.05 UIpp 24.4 0.36 nspp * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Measured Output Jitter - GR-253-CORE and T1.105.03 conformance Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Measurement Filter Limit in UI (1 UI = 6.4 ns) Signal OC-3 Interface 1 2 C19o Equivalent limit in time domain ZL30106 maximum jitter generation Units 65 kHz to 1.3 MHz 12 kHz to1.3 MHz (Category II) 500 Hz to 1.3 MHz 0.15 UIpp 0.1 UIpp 0.01 UIrms 1.5 UIpp 0.96 0.64 64 9.65 0.22 0.22 24 0.22 nspp nspp psrms nspp 3 * Supply voltage and operating temperature are as per Recommended Operating Conditions. 44 Zarlink Semiconductor Inc. ZL30106 Data Sheet Performance Characteristics*: Measured Output Jitter - G.813 conformance (Option 1 and Option 2) ITU-T G.813 Jitter Generation Requirements Jitter Measurement Filter Limit in UI (1 UI = 6.4 ns) Signal Equivalent limit in time domain ZL30106 maximum jitter generation Units STM-1 Option 1 Interface 1 2 C19o 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz 0.1 UIpp 0.5 UIpp 0.1 UIpp 0.64 3.22 0.22 0.22 nspp nspp nspp STM-1 Option 2 Interface 3 C19o 12 kHz to1.3 MHz 0.64 0.22 * Supply voltage and operating temperature are as per Recommended Operating Conditions. 45 Zarlink Semiconductor Inc. ZL30106 Performance Characteristics* - Unfiltered Jitter Generation Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C1.5o (1.544 MHz) C2o (2.048 MHz) C3o (3.088 MHz) C4o (4.096 MHz) C6o (6.312 MHz) C8o (8.192 MHz) C8.4o (8.448 MHz) C16o (16.384 MHz) C19o (19.44 MHz) C32o (32.768 MHz) C34o (34.368 MHz) C44o (44.736 MHz) C65o (65.536 MHz) F2ko (2 kHz) F4o (8 kHz) F8o (8 kHz) F16o (8 kHz) F32o (8 kHz) F65o (8 kHz) Max. [nspp] 0.45 0.47 0.53 0.42 0.58 0.42 0.55 0.56 0.42 0.46 0.56 0.60 0.49 0.40 0.43 0.43 0.44 0.43 0.46 Notes Data Sheet * Supply voltage and operating temperature are as per Recommended Operating Conditions. 8.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. 46 Zarlink Semiconductor Inc. c Zarlink Semiconductor 2002 All rights reserved. Package Code Previous package codes ISSUE ACN DATE APPRD. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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